FIG. 3 is a diagram illustrating the structure of an output portion in a prior art charge transfer device. In FIG. 3, reference numeral 1 designates a p type semiconductor substrate. An n.sup.- type semiconductor region 2 serving as a signal charge transfer region is disposed in a predetermined region of the substrate 1. An n.sup.+ type semiconductor region 3 serving as a charge storage region is disposed in a predetermined region of the substrate 1 and connected to the n.sup.- type semiconductor region 2. An n.sup.+ type semiconductor region 5 serving as a reset drain region is disposed in a region of the substrate 1 spaced from the n.sup.+ type semiconductor region 3 by a region of the substrate 1 beneath a reset gate 8. A reset drain (RD) terminal 4 is connected to the n.sup.+ type semiconductor region 5. To final stage gates 6a and 6b of a CCD driving gate, a final stage input terminal 6' is commonly connected. An output gate terminal 7' is connected to an output gate 7. A silicon dioxide film 9 covers the entire surface of the device. A source follower amplifier 10 comprising enhancement transistors Q1 and Q3 and depletion transistors Q2 and Q4 is connected to the n.sup.+ type semiconductor region 3. Reference numerals 11 and 12 designate a signal output terminal and a power supply terminal, respectively, of the source follower amplifier 10.
FIGS. 4(a)-4(d) and 5(a)-5(e) are diagrams explaining the operation of the output portion of the charge transfer device of FIG. 3. FIGS 4(a) to 4(d) are diagrams showing pulse signals applied to each gate of FIG. 3 and the potential variation at the output terminal 11 of the source follower amplifier 10. FIG. 5(a) is a schematic view showing the output portion of FIG. 3 and FIGS. 5(b) to 5(e) are diagrams showing the potential at each region of FIG. 5(a) at times t.sub.1 to t.sub.4 of FIGS. 4(a)-4(d).
In FIG. 5(a), the same reference numerals as those of FIG. 3 designate the same or corresponding parts. Reference numeral 51 designates signal charges and reference numeral 52 designates an electron. An n.sup.+ type semiconductor region 53 corresponds to the n.sup.+ semiconductor region 3 described above. Reference numeral 8' designates a reset gate terminal.
A description is given of the operation.
In FIG. 3, signal charges are transferred inside the n.sup.- type semiconductor region 2 from right to left synchronized with a clock pulse applied to the CCD gate. Signal charges that have finally reached the n.sup.+ type semiconductor region 3 vary the potential of the n.sup.+ type semiconductor region 3. The variation of the potential is detected by the source follower amplifier 10 provided on the p type semiconductor substrate 1. When an external voltage is applied to the reset gate 8, signal charges stored in the n.sup.+ type semiconductor region 3 are transferred and drained into the n.sup.+ type semiconductor region 5, whereby the device is reset.
The above-described operation is accomplished by applying input pulses shown in FIGS. 4(a)-4(d) to respective terminals. FIGS. 5(b) to 5(e) are diagrams illustrating the potential at times t.sub.1 to t.sub.4, respectively. As shown in FIG. 5(b), charges stored in the n.sup.+ type semiconductor region 53, which is going to be reset, flow into the n.sup.+ type semiconductor region 5 at time t.sub.1. Also following signal charges 51 are stored beneath the final stage driving gate 6a. A constant dc voltage is applied to the output gate terminal 7' so that the potential beneath the output gate 7 does not vary throughout times t.sub.1 to t.sub.4.
At time t.sub.2 when the reset gate terminal 8' is low, the potential against the flow of electrons of the region under the reset gate 8 rises and the potential of the n.sup.+ type semiconductor region 53 surrounded by the potential barrier is in a floating state. The potential of the n.sup.+ type semiconductor region 53 is affected by the variation of potential of the reset gate 8 via the capacitance from time t.sub.1 to t.sub.2 and the potential varies from the reset potential V.sub.R to the potential V.sub.F as shown in FIG. 4(a).
At time t.sub.3, signal charges 51 are drained into the n.sup.+ semiconductor region 53. At this time the final stage driving gate terminal 6' is low. The potential of the n.sup.+ semiconductor region 53 takes a value corresponding to the amount of signal charges. Then, the variation in the potential is detected by the source follower amplifier 10 of FIG. 3.
At time t.sub.4, the potential returns to the reset state of time t.sub.1.
The output portion of the charge transfer device having the above described structure involves a problem of reset noise which inevitably occurs during the reset operation.
As shown in FIGS. 5(b) and 5(e), at the time of reset (t.sub.1 and t.sub.4), signal charges at the n .sup.+ type semiconductor region 53 are not completely transferred to the reset drain region 5, and this causes the potential of the region 53 to fluctuate after the reset operation. This fluctuation produces a fluctuation of V.sub.R shown in FIG. 4(a), which results in noise. The cause of incomplete resetting of signal charges resides in the region 53 having a high dopant concentration. When the dopant concentration of the region 53 is lowered, enabling a complete charge depletion of the region 53, the variation of the potential V.sub.R and accordingly the reset noise can be eliminated.
However, in the prior art structure in which a wiring contact to the region 53 is made via a contact hole, charges are supplied from the input gate electrode of the source follower amplifier 10. Therefore, it is impossible to realize complete depletion.
FIGS. 8(a) to 8(c) are a perspective view partially sectioned a plan view, and a cross-sectional view, respectively, illustrating another prior art charge transfer device which reduces reset noise, disclosed in IEDM, 1989, pp.173 to 176. In the figures, reference numeral 80 designates an n type semiconductor substrate. A p-well 81 is formed in the substrate 80 and an n.sup.- type semiconductor charge storage region 83 is formed thereon surrounded by a p.sup.+ type semiconductor region 82. A drain terminal 86 and a source terminal 85 are connected to the p.sup.+ type semiconductor region 82 and a p.sup.+ type semiconductor region 84, respectively. Reference numeral 87 designates a hole current.
In the prior art device, the dopant concentration of the charge storage region 83 is lowered so as to enable complete depletion of this region. Electrodes 85 and 86 for reading signals are not directly connected to the charge storage region 83. Instead, it is constructed such that the amount of the stored charge at the charge storage region 83 changes the width of the depletion layer that is produced in the vicinity of the boundary between the charge storage region 83 and the p type well 81 beneath the region 83 and that is detected by the current flowing in a channel comprising the depletion layer, between the p.sup.+ type semiconductor region 82 and the p.sup.+ type semiconductor region 84. In other words, the signal charges are detected from the current flowing in the FET comprising the charge storage region 83 serving as a ring-junction-gate, the p.sup.+ type semiconductor region 82 serving as a source, and the p.sup.+ type semiconductor region 84 serving as a drain. Accordingly, charges are not supplied from the electrode during the reset operation and the charge storage region is completely depleted, thereby reducing the reset noise.
Thus, in the second prior art charge transfer device, a p-well structure is required for producing an FET which detects the amount of signal charges, resulting in a structure that is extremely complicated.